* PSpice Model Editor - Version 9.2 *$ * * AD22057T SPICE Macro-model Rev. A, 11/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | A1 out * | | | | | A2 in * | | | | | | offset * | | | | | | | output * | | | | | | | | .SUBCKT AD22057T/AD 1 2 99 50 30 31 40 49 * * A1 INPUT ATTENUATORS, GAIN, AND OFFSET RESISTORS * R1 1 3 200K R2 2 4 200K RS1 3 16 1K RS2 4 18 1K R3 3 5 41K R4 4 6 41K R5 5 6 2.566K TC=-134U R6 5 50 250 R7 6 50 250 R8 5 19 9K R9 6 7 10K R10 19 40 2K R11 19 50 2K R12 7 30 100K R16 7 50 10K C1 16 50 5P C2 17 50 5P * * A1 INPUT STAGE AND POLE AT 1MHZ * I1 99 8 7.55U Q1 11 16 9 QP 1 Q2 12 17 10 QP 1 R21 11 50 6.89671K R22 12 50 6.89671K R23 8 9 .335 R24 8 10 .335 C3 11 12 11.5P EOS 61 17 POLY(1) 33 0 -220.5U 0.537 ETC 18 61 POLY(1) 60 0 -49.665M 1 ITC 0 60 49.665U RTC 60 0 1E3 TC=-102U * * GAIN STAGE AND DOMINANT POLE AT 400HZ * EREF 98 50 POLY(2) 99 0 50 0 0 0.5 0.5 G1 98 13 12 11 144.997U R25 13 98 6.89671E6 C4 13 98 57.6923P D1 13 99 DX D2 50 13 DX * * COMMON MODE STAGE WITH ZERO AT 1.78KHZ * ECM 32 0 POLY(2) 1 0 2 0 0 0.5 0.5 R28 32 33 1E6 R29 33 0 10 CCM 32 33 89.5P * * NEGATIVE ZERO AT 0.6MHZ * E1 23 98 13 98 1E6 R26 23 24 1E3 R27 24 98 1E-3 FNZ 23 24 VNZ -1 ENZ 25 98 23 24 1 VNZ 26 98 DC 0 CNZ 25 26 265P * * POLE AT 5MHZ * G2 98 20 24 98 1E-6 R30 20 98 1E6 C5 20 98 32F * * A1 OUTPUT STAGE * EIN1 99 27 POLY(1) 20 98 1.4995 1.124 Q216 50 27 28 QP375 3.444 Q218 7 29 99 QP350 9.913 R31 28 29 27K I2 99 29 4.75U * * A2 INPUT STAGE * I3 99 34 2.516667U Q3 35 31 37 QP 1 Q4 36 39 38 QP 1 R32 35 50 106.103K R33 36 50 106.103K R34 34 37 85.414K R35 34 38 85.414K R13 40 41 20K R14 41 50 20K R15 41 49 10K R17 39 41 95K * * A2 1ST GAIN STAGE AND SLEW RATE * G3 98 42 36 35 30.159U R36 42 98 1E6 E2 99 43 POLY(1) 99 98 -0.473 1 E3 44 50 POLY(1) 98 50 -0.473 1 D3 42 43 DX D4 44 42 DX * * A2 2ND GAIN STAGE AND DOMINANT POLE AT 12HZ * G4 98 45 42 98 2.5U R37 45 98 132.629E6 C7 45 98 100P D5 45 59 DX D6 55 45 DX VC1 59 99 5 VC2 50 55 5 * * NEGATIVE ZERO AT 1MHZ * E4 51 98 45 98 1E6 R38 51 52 1E6 R39 52 98 1 FNZ2 51 52 VNZ2 -1 ENZ2 53 98 51 52 1 VNZ2 54 98 0 CNZ2 53 54 159F * * A2 OUTPUT STAGE * ISY 99 50 169U EIN2 99 56 POLY(1) 52 98 1.73166 112.132E-3 RIN 46 56 10K Q316 50 46 47 QP375 1.778 Q310 50 47 48 QP375 5.925 Q318 49 48 57 50 QP350 9.913 I4 99 47 4.75U I5 99 48 9.5U VSC 99 57 0 FSC 58 99 VSC 1 QSC 46 58 99 QP350 1 RSC 99 58 56 * * MODELS USED * .MODEL QP350 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350 +RC=200) .MODEL QP375 PNP(IS=1.4E-15 CJE=.01P CJC=.05P RE=20 RC=400 RB=100) .MODEL QP AKO:QP350 PNP(BF=150 VA=100) .MODEL DX D(CJO=1F RS=.1) .ENDS * *$ * AD22050T SPICE Macro-model Rev. A, 9/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | A1 out * | | | | | A2 in * | | | | | | offset * | | | | | | | output * | | | | | | | | .SUBCKT AD22050T/AD 1 2 99 50 30 31 40 49 * * A1 INPUT ATTENUATORS, GAIN, AND OFFSET RESISTORS * R1 1 3 200K R2 2 4 200K RS1 3 16 1K RS2 4 18 1K R3 3 5 41K R4 4 6 41K R5 5 6 2.566K TC=-134U R6 5 50 250 R7 6 50 250 R8 5 19 9K R9 6 7 10K R10 19 40 2K R11 19 50 2K R12 7 30 100K R16 7 50 10K C1 16 50 5P C2 17 50 5P * * A1 INPUT STAGE AND POLE AT 1MHZ * I1 99 8 7.55U Q1 11 16 9 QP 1 Q2 12 17 10 QP 1 R21 11 50 6.89671K R22 12 50 6.89671K R23 8 9 .335 R24 8 10 .335 C3 11 12 11.5P EOS 61 17 POLY(1) 33 0 -225.534U 0.537 ETC 18 61 POLY(1) 60 0 -49.665M 1 ITC 0 60 49.665U RTC 60 0 1E3 TC=-102U * * GAIN STAGE AND DOMINANT POLE AT 400HZ * EREF 98 50 POLY(2) 99 0 50 0 0 0.5 0.5 G1 98 13 12 11 144.997U R25 13 98 6.89671E6 C4 13 98 57.6923P D1 13 99 DX D2 50 13 DX * * COMMON MODE STAGE WITH ZERO AT 1.78KHZ * ECM 32 0 POLY(2) 1 0 2 0 0 0.5 0.5 R28 32 33 1E6 R29 33 0 10 CCM 32 33 89.5P * * NEGATIVE ZERO AT 0.6MHZ * E1 23 98 13 98 1E6 R26 23 24 1E3 R27 24 98 1E-3 FNZ 23 24 VNZ -1 ENZ 25 98 23 24 1 VNZ 26 98 DC 0 CNZ 25 26 265P * * POLE AT 5MHZ * G2 98 20 24 98 1E-6 R30 20 98 1E6 C5 20 98 32F * * A1 OUTPUT STAGE * EIN1 99 27 POLY(1) 20 98 1.5072 1.124 Q216 50 27 28 QP375 3.444 Q218 7 29 99 QP350 9.913 R31 28 29 27K I2 99 29 4.75U * * A2 INPUT STAGE * I3 99 34 2.516667U Q3 35 31 37 QP 1 Q4 36 39 38 QP 1 R32 35 50 106.103K R33 36 50 106.103K R34 34 37 85.414K R35 34 38 85.414K R13 40 41 20K R14 41 50 20K R15 41 49 10K R17 39 41 95K * * A2 1ST GAIN STAGE AND SLEW RATE * G3 98 42 36 35 30.159U R36 42 98 1E6 E2 99 43 POLY(1) 99 98 -0.473 1 E3 44 50 POLY(1) 98 50 -0.473 1 D3 42 43 DX D4 44 42 DX * * A2 2ND GAIN STAGE AND DOMINANT POLE AT 12HZ * G4 98 45 42 98 2.5U R37 45 98 132.629E6 C7 45 98 100P D5 45 59 DX D6 55 45 DX VC1 59 99 5 VC2 50 55 5 * * NEGATIVE ZERO AT 1MHZ * E4 51 98 45 98 1E6 R38 51 52 1E6 R39 52 98 1 FNZ2 51 52 VNZ2 -1 ENZ2 53 98 51 52 1 VNZ2 54 98 0 CNZ2 53 54 159F * * A2 OUTPUT STAGE * ISY 99 50 169U EIN2 99 56 POLY(1) 52 98 1.6901 112.132E-3 RIN 46 56 10K Q316 50 46 47 QP375 1.778 Q310 50 47 48 QP375 5.925 Q318 49 48 57 50 QP350 9.913 I4 99 47 4.75U I5 99 48 9.5U VSC 99 57 0 FSC 58 99 VSC 1 QSC 46 58 99 QP350 1 RSC 99 58 56 * * MODELS USED * .MODEL QP350 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350 +RC=200) .MODEL QP375 PNP(IS=1.4E-15 CJE=.01P CJC=.05P RE=20 RC=400 RB=100) .MODEL QP AKO:QP350 PNP(BF=150 VA=100) .MODEL DX D(CJO=1F RS=.1) .ENDS * PSpice Model Editor - Version 9.2 *$ .SUBCKT AD604AN 251 254 253 1 150 256 101 102 30 99 50 *node assignments * in fbk pao vgn vref vocm +dsx -dsx vout v+ v- *** AD604an SPICE model, rev A, 12/97 * written by Steve Reine/Eberhard Brunner 12/97 * preamp including noise vs Vgn enoise 251 252 poly(2) 601 0 604 0 0 1 1 rin 252 0 300e3 epao 253 0 poly(2) 252 0 255 0 0 1e6 -1e6 rinfb1 253 254 40 rinfb2 254 255 32 rinfb3 255 0 8 rn1 600 0 0.034 vn1 600 0 0 fn1 601 0 vn1 1 rn2 601 0 1 en2 602 0 poly(1) 1 0 0.67 -0.1 dn1 602 603 dn vn3 603 0 0 fn2 604 0 vn3 1 rn3 604 0 1 * vref inverter vinv 202 0 1 einv 201 0 202 203 10e6 evmult 203 0 poly(2) 201 0 150 0 0 0 0 0 1 * vocm input rvocm1 99 256 200k rvocm2 256 0 200k eocm 100 0 256 0 1 * R/1.5R attenuation ladder ra1 101 103 96 ra2 103 100 144 ra3 100 104 144 ra4 102 104 96 ra5 103 105 96 ra6 105 100 144 ra7 100 106 144 ra8 104 106 96 ra9 105 107 96 ra10 107 100 144 ra11 100 108 144 ra12 106 108 96 ra13 107 109 96 ra14 109 100 144 ra15 100 110 144 ra16 108 110 96 ra17 109 111 96 ra18 111 100 144 ra19 100 112 144 ra20 110 112 96 ra21 111 113 96 ra22 113 100 144 ra23 100 114 144 ra24 112 114 96 ra25 113 115 96 ra26 115 100 144 ra27 100 116 144 ra28 114 116 96 ra29 115 100 175 ra30 100 116 175 * input tanh pairs with gain controlled * by current steering ladder q11 21 101 22 qn1 q12 20 102 22 qn1 4 q13 21 101 42 qn1 4 q14 20 102 42 qn1 f22a 22 50 vl2 4 f22b 42 50 vl2 4 q21 21 103 23 qn1 q22 20 104 23 qn1 4 q23 21 103 43 qn1 4 q24 20 104 43 qn1 f23a 23 50 vl3 4 f23b 43 50 vl3 4 q31 21 105 24 qn1 q32 20 106 24 qn1 4 q33 21 105 44 qn1 4 q34 20 106 44 qn1 f24a 24 50 vl4 4 f24b 44 50 vl4 4 q41 21 107 25 qn1 q42 20 108 25 qn1 4 q43 21 107 45 qn1 4 q44 20 108 45 qn1 f25a 25 50 vl5 4 f25b 45 50 vl5 4 q51 21 109 26 qn1 q52 20 110 26 qn1 4 q53 21 109 46 qn1 4 q54 20 110 46 qn1 f26a 26 50 vl6 4 f26b 46 50 vl6 4 q61 21 111 27 qn1 q62 20 112 27 qn1 4 q63 21 111 47 qn1 4 q64 20 112 47 qn1 f27a 27 50 vl7 4 f27b 47 50 vl7 4 q71 21 113 28 qn1 q72 20 114 28 qn1 4 q73 21 113 48 qn1 4 q74 20 114 48 qn1 f28a 28 50 vl8 4 f28b 48 50 vl8 4 q81 21 115 29 qn1 q82 20 116 29 qn1 4 q75 21 115 49 qn1 4 q76 20 116 49 qn1 f29a 29 50 vl9 4 f29b 49 50 vl9 4 * gaussian transistor current steering ladder ib1 2 50 495e-6 ib2 9 50 495e-6 ggn 9 2 poly(2) 201 0 1 0 -430e-6 0 0 0 680e-6 i1 19 50 350e-6 i2 0 2 100e-6 i3 0 3 51e-6 i4 0 4 51e-6 i5 0 5 51e-6 i6 0 6 51e-6 i7 0 7 51e-6 i8 0 8 51e-6 i9 0 9 100e-6 rl1 99 2 8k rl2 99 9 8k rl3 2 3 1.8k rl4 3 4 1.8k rl5 4 5 1.8k rl6 5 6 1.8k rl7 6 7 1.8k rl8 7 8 1.8k rl9 8 9 1.8k ql2 32 2 19 qn1 ql3 33 3 19 qn1 ql4 34 4 19 qn1 ql5 35 5 19 qn1 ql6 36 6 19 qn1 ql7 37 7 19 qn1 ql8 38 8 19 qn1 ql9 39 9 19 qn1 vl2 99 32 0 vl3 99 33 0 vl4 99 34 0 vl5 99 35 0 vl6 99 36 0 vl7 99 37 0 vl8 99 38 0 vl9 99 39 0 * feedback gm stage q01 921 900 302 qn1 q02 920 60 302 qn1 4 q03 921 900 303 qn1 4 q04 920 60 303 qn1 io1a 302 50 1.068e-3 io2a 303 50 1.068e-3 * distributed and feedback gain stages are summed together vgain1 99 20 0 vgain2 99 21 0 vgain3 99 920 0 vgain4 99 921 0 * and added to create fgm1 stage fgm1 99 31 vgain2 0.94 fgm2 99 31 vgain1 -0.94 fgm3 99 31 vgain4 1 fgm4 99 31 vgain3 -1 * second gm stage + output stage cgm 31 100 2.45e-12 rgm 31 100 92k dbuf1 31 52 dg dbuf2 53 31 dg vcl1 99 52 1.55 vcl2 53 50 1.55 gbuf 100 51 31 100 1e-2 rbuf 100 51 1e2 dcl1 51 54 dg dcl2 55 51 dg vcl3 30 54 0.716 vcl4 55 30 0.716 gout1 30 99 99 51 0.5 gout2 30 50 50 51 0.5 rout1 30 99 2 rout2 30 50 2 rfb1 30 60 820 rfb2 60 100 20 rfb2a 900 100 1e-3 .model dg d() .model dn d(af=1 kf=1e-8) .model qn1 npn(bf=1e6) .ends ad604an *$ *** AD605an SPICE model, rev A *** ADI copywrite 1998 *** SMR/1-98 *node assignments * vgn vref vocm +dsx -dsx fdbk vout v+ v- .SUBCKT AD605AN 1 150 256 101 102 251 30 99 50 * vref inverter vinv 202 0 1 einv 201 0 202 203 10e6 evmult 203 0 poly(2) 201 0 150 0 0 0 0 0 1 * vocm input rvocm1 99 256 200k rvocm2 256 0 200k eocm 100 0 256 0 1 * R/1.5R attenuation ladder ra1 101 103 96 ra2 103 100 144 ra3 100 104 144 ra4 102 104 96 ra5 103 105 96 ra6 105 100 144 ra7 100 106 144 ra8 104 106 96 ra9 105 107 96 ra10 107 100 144 ra11 100 108 144 ra12 106 108 96 ra13 107 109 96 ra14 109 100 144 ra15 100 110 144 ra16 108 110 96 ra17 109 111 96 ra18 111 100 144 ra19 100 112 144 ra20 110 112 96 ra21 111 113 96 ra22 113 100 144 ra23 100 114 144 ra24 112 114 96 ra25 113 115 96 ra26 115 100 144 ra27 100 116 144 ra28 114 116 96 ra29 115 100 175 ra30 100 116 175 * input tanh pairs with gain controlled * by current steering ladder q11 21 101 22 qn1 q12 20 102 22 qn1 4 q13 21 101 42 qn1 4 q14 20 102 42 qn1 f22a 22 50 vl2 4 f22b 42 50 vl2 4 q21 21 103 23 qn1 q22 20 104 23 qn1 4 q23 21 103 43 qn1 4 q24 20 104 43 qn1 f23a 23 50 vl3 4 f23b 43 50 vl3 4 q31 21 105 24 qn1 q32 20 106 24 qn1 4 q33 21 105 44 qn1 4 q34 20 106 44 qn1 f24a 24 50 vl4 4 f24b 44 50 vl4 4 q41 21 107 25 qn1 q42 20 108 25 qn1 4 q43 21 107 45 qn1 4 q44 20 108 45 qn1 f25a 25 50 vl5 4 f25b 45 50 vl5 4 q51 21 109 26 qn1 q52 20 110 26 qn1 4 q53 21 109 46 qn1 4 q54 20 110 46 qn1 f26a 26 50 vl6 4 f26b 46 50 vl6 4 q61 21 111 27 qn1 q62 20 112 27 qn1 4 q63 21 111 47 qn1 4 q64 20 112 47 qn1 f27a 27 50 vl7 4 f27b 47 50 vl7 4 q71 21 113 28 qn1 q72 20 114 28 qn1 4 q73 21 113 48 qn1 4 q74 20 114 48 qn1 f28a 28 50 vl8 4 f28b 48 50 vl8 4 q81 21 115 29 qn1 q82 20 116 29 qn1 4 q75 21 115 49 qn1 4 q76 20 116 49 qn1 f29a 29 50 vl9 4 f29b 49 50 vl9 4 * gaussian transistor current steering ladder ib1 2 50 495e-6 ib2 9 50 495e-6 ggn 9 2 poly(2) 201 0 1 0 -430e-6 0 0 0 680e-6 i1 19 50 350e-6 i2 0 2 100e-6 i3 0 3 51e-6 i4 0 4 51e-6 i5 0 5 51e-6 i6 0 6 51e-6 i7 0 7 51e-6 i8 0 8 51e-6 i9 0 9 100e-6 rl1 99 2 8k rl2 99 9 8k rl3 2 3 1.8k rl4 3 4 1.8k rl5 4 5 1.8k rl6 5 6 1.8k rl7 6 7 1.8k rl8 7 8 1.8k rl9 8 9 1.8k ql2 32 2 19 qn1 ql3 33 3 19 qn1 ql4 34 4 19 qn1 ql5 35 5 19 qn1 ql6 36 6 19 qn1 ql7 37 7 19 qn1 ql8 38 8 19 qn1 ql9 39 9 19 qn1 vl2 99 32 0 vl3 99 33 0 vl4 99 34 0 vl5 99 35 0 vl6 99 36 0 vl7 99 37 0 vl8 99 38 0 vl9 99 39 0 * feedback gm stage q01 921 900 302 qn1 q02 920 60 302 qn1 4 q03 921 900 303 qn1 4 q04 920 60 303 qn1 io1a 302 50 1.068e-3 io2a 303 50 1.068e-3 * distributed and feedback gain stages are summed together vgain1 99 20 0 vgain2 99 21 0 vgain3 99 920 0 vgain4 99 921 0 * and added to create fgm1 stage fgm1 99 31 vgain2 0.94 fgm2 99 31 vgain1 -0.94 fgm3 99 31 vgain4 1 fgm4 99 31 vgain3 -1 * second gm stage + output stage cgm 31 100 2.45e-12 rgm 31 100 92k dbuf1 31 52 dg dbuf2 53 31 dg vcl1 99 52 1.55 vcl2 53 50 1.55 gbuf 100 51 31 100 1e-2 rbuf 100 51 1e2 dcl1 51 54 dg dcl2 55 51 dg vcl3 30 54 0.716 vcl4 55 30 0.716 gout1 30 99 99 51 0.5 gout2 30 50 50 51 0.5 rout1 30 99 2 rout2 30 50 2 rfb1 30 251 3.36k rfb2 251 60 820 rfb3 60 100 20 rfb2a 900 100 1e-3 .model dg d() .model dn d(af=1 kf=1e-8) .model qn1 npn(bf=1e6) .ends ad605an *$ * AD623 SPICE Macromodel Rev. B 9/2000 * JCH / ADI * TRW / ADI * Copyright 1999 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * non-inverting input * | inverting input * | | +Rg * | | | -Rg * | | | | positive supply * | | | | | negative supply * | | | | | | output * | | | | | | | reference * | | | | | | | | .SUBCKT AD623 IN+ IN- Rg+ Rg- 99 50 OUT REF QIN1 50 IN+ A3 QPI1 QIN2 50 IN- A4 QPI2 IBIAS1 99 A3 2u IBIAS2 99 A4 2u R1 Rg+ 103 50k R2 Rg- 104 50k CMR Rg+ 99 0.5p R3 104 202 50k R4 103 201 50k *Output stage common-mode error R5 201 REF 50.004k R6 202 OUT 49.996k *X1 201 202 99 50 OUT Inamp_output *X2 A3 Rg+ 99 50 103 Inamp_input *X3 A4 Rg- 99 50 104 Inamp_input *Quiescent current correction Icor 99 50 1.25e-4 * INPUT STAGE * Q1B B4 B3 B5 QPI Q2B B6 202 b7 QPI RC1B 50 B4 8.5k RC2B 50 B6 8.5k RE1B B5 B8 3.3k RE2B B7 B8 3.3k ENOISB 201 B3 B53 98 1 D1B B3 99 DX D2B 50 B3 DX IBIASB 99 B8 10u * * INTERNAL VOLTAGE REFERENCE * EREF1 98 97 99 0 0.5 EREF2 97 0 50 0 0.5 * * VOLTAGE NOISE STAGE * DN1B B51 B52 DNOI1 VN1B B51 98 0.64 VMEASB B52 98 0 RNOI1B B52 98 1 F1B B53 98 VMEASB 1 RNOI2B B53 98 1 * * INTERMEDIATE GAIN STAGE WITH POLE = 578kHz * G1B 98 B20 B4 B6 1E-3 RP1B 98 B20 550 CP1B 98 B20 500p * * INTERMEDIATE GAIN STAGE WITH POLE = 900kHz * G2B 98 B21 B4 B6 1E-3 RP2B 98 B21 500 CP2B 98 B21 354p * * GAIN STAGE WITH DOMINANT POLE * G4B 98 B30 B21 98 3.65E-3 RG1B B30 98 25k CF1B B30 OUT 0.275n D5B B31 99 DX D6B 50 B32 DX V1B B31 B30 0.6 V2B B30 B32 0.6 * * OUTPUT STAGE * Q3B OUT B42 B43 QPOX Q4B OUT B44 B46 QNOX RO3B 99 B43 30 RO4B B46 50 30 VBI01B 99 B41 0.5965 VBIO2B B47 50 0.5965 EO3B B41 B42 98 B30 10 EO4B B44 B47 B30 98 10 * * INPUT STAGE * Q1C C4 C5 C8 QPI Q2C C6 RG+ C8 QPI RC1C 50 C4 8.5k RC2C 50 C6 8.5k ENOIC A3 C5 C53 98 1 D1C C3 99 DX D2C 50 C3 DX IBIASC 99 C8 10u * * * VOLTAGE NOISE STAGE * DN1C C51 C52 DNOI1 VN1C C51 98 0.64 VMEASC C52 98 0 RNOI1C C52 98 1e-4 F1C C53 98 VMEASC 1 RNOI2C C53 98 1 * * INTERMEDIATE GAIN STAGE * G1C 98 C20 C4 C6 1E-3 RP1C 98 C20 4.67k * * GAIN STAGE WITH DOMINANT POLE * G4C 98 C30 C20 98 2E-3 RG1C C30 98 125k CF1C C30 103 2.5n D5C C31 99 DX D6C 50 C32 DX V1C C31 C30 0.6 V2C C30 C32 0.6 * * OUTPUT STAGE * Q3C 103 C42 C43 QPOX Q4C 103 C44 C46 QNOX RO3C 99 C43 30 RO4C C46 50 30 VBI01C 99 C41 0.5965 VBIO2C C47 50 0.5965 EO3C C41 C42 98 C30 5 EO4C C44 C47 C30 98 5 * * INPUT STAGE * Q1D D4 D5 D8 QPI Q2D D6 RG- D8 QPI RC1D 50 D4 8.5k RC2D 50 D6 8.5k ENOID A4 D5 D53 98 1 D1D D3 99 DX D2D 50 D3 DX IBIASD 99 D8 10u * * * VOLTAGE NOISE STAGE * DN1D D51 D52 DNOI1 VN1D D51 98 0.64 VMEASD D52 98 0 RNOI1D D52 98 1e-4 F1D D53 98 VMEASD 1 RNOI2D D53 98 1 * * INTERMEDIATE GAIN STAGE * G1D 98 D20 D4 D6 1E-3 RP1D 98 D20 4.67k * * GAIN STAGE WITH DOMINANT POLE * G4D 98 D30 D20 98 2E-3 RG1D D30 98 125k CF1D D30 104 2.5n D5D D31 99 DX D6D 50 D32 DX V1D D31 D30 0.6 V2D D30 D32 0.6 * * OUTPUT STAGE * Q3D 104 D42 D43 QPOX Q4D 104 D44 D46 QNOX RO3D 99 D43 30 RO4D D46 50 30 VBI01D 99 D41 0.5965 VBIO2D D47 50 0.5965 EO3D D41 D42 98 D30 5 EO4D D44 D47 D30 98 5 * .MODEL QPI PNP(VAF=100) .MODEL QNOX NPN(IS=6E-15,VAF=120,RC=50) .MODEL QPOX PNP(IS=6E-15,BF=112,VAF=120,RC=50) .MODEL DX D(IS=1E-16) .MODEL DNOI1 D(AF=1.5, KF=6E-10) .MODEL DNOI2 D(KF=1E-8) .MODEL QPI1 PNP(VAF=100) .MODEL QPI2 PNP(VAF=99.3) .ENDS AD623 *$ * OP184 SPICE Macro-model 11/95 / Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Changed input transistor betas to conform to final data sheet * Ios typical spec of 60nA. * * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP184 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 IOS 2 1 5E-9 CIN 1 2 2E-12 GN1 98 1 (17,98) 1E-3 GN2 98 2 (23,98) 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 100HZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 1.592E-3 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 (20,98) 1E6 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 (27,28) 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 (28,98) 1 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 (29,98) 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.276E-3 GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) .ENDS OP184 *$ * OP186 SPICE Macro-model Typical Values * 2/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP186 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX RC1 4 50 100E3 RC2 6 50 100E3 RE1 3 8 6.452E3 RE2 5 8 6.452E3 C1 4 6 50E-15 I1 99 8 1E-6 EOS 7 2 POLY(2) (12,98) (73,98) 800E-6 1 1 IOS 1 2 50E-12 V1 99 9 0.9 V2 99 10 0.9 D1 3 9 DX D2 5 10 DX * * CMRR 90dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 11 12 1.59E6 CCM1 11 12 100E-12 RCM2 12 98 50 * * PSRR=100dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 15.9 * * INTERNAL VOLTAGE REFERENCE * * RSY1 99 91 10E6 * RSY2 50 90 10E6 * VSN1 91 90 DC 0 * EREF 98 0 (90,0) 1 EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 2E-6 .1E-6 * * POLE AT 600kHz; ZERO AT 900kHz * G1 98 20 (4,6) 11.3E-6 R1 20 98 88.46E3 R2 20 21 176.8E3 C2 21 98 1E-12 * * GAIN STAGE * G4 98 30 (20,98) 19.54E-6 R7 30 98 111.6E6 CF 45 30 32E-12 D3 30 31 DX D4 32 30 DX V3 99 31 0.6 V4 32 50 0.6 * * OUTPUT STAGE * M1 45 46 99 99 POX L=2u W=100u M2 45 47 50 50 NOX L=2u W=98u EG1 99 46 POLY(1) (98,30) 0.82 1 EG2 47 50 POLY(1) (30,98) 0.79 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=10E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=17E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=185,KF=1.6E-12,AF=1) * .MODEL PIX2 PNP (BF=200,IS=1E-16) .MODEL DX D(IS=1E-14) .ENDS OP186 *$ * AD8012n SPICE Macro-model rev A; 2/27/98,SMR,ADI * Copyright 1998 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8012an 1 2 99 50 24 * INPUT STAGE v1 8 2 0 i1 99 5 108e-6 i2 4 50 108e-6 q1 50 3 5 qp q2 99 3 4 qn q3 99 5 8 qn q4 50 4 8 qp * input error sources fn 99 2 vn4 1e-3 ib1 2 99 3e-6 ib2 3 99 3e-6 eos 3 1 poly(1) (32,98) 1.5e-3 1 cs3 98 2 2.3e-12 cs4 98 3 2.3e-12 * first gain stage and dominant pole fgain 98 12 poly(1) v1 0 1 0 3350 r5 12 98 500k c4 12 98 2.37e-12 v3 99 13 1.68 v4 14 50 1.68 d3 12 13 dx d4 14 12 dx * secondary pole gpole 98 40 12 98 1 rpole 98 40 1 cpole 98 40 0.34e-9 * v noise generator vn1 30 98 0.555 dn1 30 31 dn1 rn1 31 98 4.2e-3 vn2 31 98 0 fn1 32 98 vn2 1 rn2 32 98 1 * i noise generation vn3 33 98 0.555 dn2 33 34 dn1 rn3 34 98 4.2e-3 vn4 34 98 0 fn2 35 98 vn4 1 rn4 35 98 1 * buffer stage g13 98 17 40 98 1e-2 rbuf 17 98 100 * reference stage eref1 98 0 poly(2) 99 0 50 0 0 0.5 0.5 * current mirroring on supplies fo3 98 300 vo1 1 vi1 311 98 0 vi2 98 312 0 dm1 300 311 dx dm2 312 300 dx * output stage r15 23 90 2 r16 23 91 2 vo1 23 24 0 vo2 99 90 0 vo3 91 50 0 fo1 0 99 poly(2) vo2 vi1 -6.67e-3 1 -1 fo2 50 0 poly(2) vo3 vi2 -6.67e-3 1 -1 rl 24 98 1e6 g11 23 90 99 17 0.5 g12 23 91 50 17 0.5 v5 19 23 0.275 v6 23 20 0.275 d5 19 17 dx d6 17 20 dx * models .model qn npn() .model qp pnp() .model dx d() .model dn1 d(af=1 kf=1e-10) .ends ad8012an *$ * AD8017 Spice Macro-model 1/12/99, Rev A * JCH/CentApps * Copyright 1999 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8017 1 2 99 50 61 ***** Input Stage q1 4 4 41 qn1 q2 3 3 41 qp1 i1 99 4 1.5e-4 i2 3 50 1.5e-4 cin1 1 88 2.4pf q3 9 4 2 qn2 q4 10 3 2 qp2 rxxa 99 4 100k rxxb 3 50 100k VT1 9 99 0 VT2 10 50 0 vos 41 1 1.8m fnoi1 1 0 vn2 1 fnoi2 2 0 vn2 1 ***** internal inoise source vbi 73 88 0.545 dn2 73 72 dninv rn3 72 88 36 vn2 72 88 0 ***** internal reference Eref 88 0 poly(2) 99 0 50 0 0 0.5 0.5 ***** gain stage/dominant pole/clamp circuitry F3 29 88 VT1 1 F4 29 88 VT2 1 r3 29 88 710k c1 29 88 1.84p vc1 99 45 1.59 vc2 46 50 1.59 dc1 29 45 dx dc2 46 29 dx ***** pole at 177MHz egain2 32 88 88 29 1 r4 32 44 1 c3 44 88 0.835n ***** buffer to output stage gbuf 34 88 44 88 1e-2 re1 34 88 100 ***** output stage fo1 88 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 88 0 vi2 88 112 0 fsy1 99 0 poly(2) visy1 vi1 6.3e-3 -1 1 fsy2 0 50 poly(2) visy2 vi2 6.3e-3 -1 1 go3 60 63 99 34 2.5 go4 64 60 34 50 2.5 r03 60 63 0.4 r04 60 64 0.4 visy1 99 63 0 visy2 64 50 0 vcd 60 61 0 do5 34 70 dx do6 71 34 dx vo1 70 60 -0.405 vo2 60 71 -0.405 .model dx d(is=1e-13 kf=6.5e-20 af=0) .model dninv d(kf=5e-14) .model qn1 npn(bf=200) .model qn2 npn(bf=200) .model qp1 pnp(bf=200) .model qp2 pnp(bf=200) .ends ad8017 *$ * AD8051 SPICE Macro-model Rev. 0 * JCH / ADI 9/22/98 * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * *THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) *CMRR IS NOT MODELED * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8051 1 2 99 50 45 * * INPUT STAGE * Q1 4 3 5 QPI Q2 6 2 7 QPI RC1 50 4 20.5k RC2 50 6 20.5k RE1 5 8 5k RE2 7 8 5k EOS 3 1 POLY(1) 53 98 1.7E-3 1 IOS 1 2 0.1u FNOI1 1 0 VMEAS2 1E-4 FNOI2 2 0 VMEAS2 1E-4 CPAR1 3 50 1.7p CPAR2 2 50 1.7p VCMH1 99 9 1 VCMH2 99 10 1 D1 5 9 DX D2 7 10 DX IBIAS 99 8 73u * * INTERNAL VOLTAGE REFERENCE * EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 GREF2 97 0 97 0 1E-6 * *VOLTAGE NOISE STAGE * DN1 51 52 DNOI1 VN1 51 98 0.61 VMEAS 52 98 0 RNOI1 52 98 6.5E-3 H1 53 98 VMEAS 1 RNOI2 53 98 1 * *CURRENT NOISE STAGE * DN2 61 62 DNOI2 VN2 61 98 0.545 VMEAS2 62 98 0 RNOI3 62 98 2E-4 * * INTERMEDIATE GAIN STAGE WITH POLE = 96MHz * G1 98 20 4 6 1E-3 RP1 98 20 550 CP1 98 20 3p * * GAIN STAGE WITH DOMINANT POLE * G4 98 30 20 98 2.6E-3 RG1 30 98 155k CF1 30 45 13.5p D5 31 99 DX D6 50 32 DX V1 31 30 0.6 V2 30 32 0.6 * * OUTPUT STAGE * Q3 45 42 99 QPOX Q4 45 44 50 QNOX EO3 99 42 POLY(1) 98 30 0.7175 0.5 EO4 44 50 POLY(1) 30 98 0.7355 0.5 * * MODELS * .MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) .MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) .MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) .MODEL DX D(IS=1E-16) .MODEL DZ D(IS=1E-14,BV=6.6) .MODEL DNOI1 D(KF=9E-10) .MODEL DNOI2 D(KF=1E-8) .ENDS AD8051 *$ * AD8138 SPICE Macro-model, JG. rev B; 11/23/99,ADI * Copyright 1999 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is non-static, will vary with gain) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, not included in this version * inoise, not included in this version * Vocm is varable and include input typical offset * distortion is not characterized * cmrr is not characterized in this version. * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output negative * | | | | | output positve * | | | | | | vocm input * | | | | | | | .SUBCKT AD8138 3a 9 99 98 71 71b 110 ****************************input stage******************************************* *****positive input left side***** I1 99 5 .4E-3 Q1 98 2 5 QX vos 3a 2 -1.95E-3 G1 13 14 5 6 5E-3 **RAIL CLIPING**** Dlim+ 14 14b dx Vlim+ 99 14b 2.836 Dlim 14c 14 dx Vlim 14c 98 2.836 Dlim- 13b 13 DX Vlim- 13b 98 2.836 Dlim-B 13 13C dx Vlim-B 99 13C 2.836 ** VOCM INPUT RAIL CLIPING**** DOCMa 100 100A dx VOCMa 99 100A 1.899 DOCMb 100b 100 DX VOCMb 100b 98 1.899 *****negative input right side***** I2 99 6 .4E-3 Q2 98 9 6 QX * ***********Input capacitance/impedance******* Cin 3a 9 1p ***************************************pole, zero pole stage******************************************** c1 14 13 1.7p c2 13 0 .6p c3 14 0 .6p r11 13 0 250k r12 14 0 250k *********pole zero stage( POSITIVE SIDE)******* gp1 0 75 14 0 1 RP1 75 0 1 CP1 75 0 .38E-9 *********pole zero stage( NEGATIVE SIDE)******* gp2 0 76 13 0 1 RP2 76 0 1 CP2 76 0 .38E-9 **********output stage Positive side************* D17 76 84 DX VO1 84 70 .177V VO2 70 85 .177V D16 85 76 DX G30 70 99c 99 76 91E-3 G31 98c 70 76 98 91E-3 RO30 70 99c 11 RO31 98c 70 11 VIOUT1 99 99c 0V VIOUT2 98 98c 0V VIOUT3 70 71 0V ********** Output Stage Negative side ************* D17b 75 84b DX VO1b 84b 70b .177V VO2b 70b 85b .177V D16b 85b 75 DX G30b 70b 99d 99 75 91E-3 G31b 98d 70b 75 98 91E-3 RO30b 70b 99d 11 RO31b 98d 70b 11 VIOUTB1 99 99d 0V VIOUTB2 98d 98 0V VIOUTB3 70b 71b 0V *********VOCM STAGE************************* Gocm_a 0 75 110 0 1 Gocm_b 0 76 110 0 1 Rocm1 99 100 400k Rocm2 100 98 400k Voffset 100 110 -1E-3 ********CURRENT MIRROR TO SUPPLIES POSITVIE SIDE********* FO1 0 99 poly(2) VIOUT1 VI1 -19.803E-3 1 -1 FO2 0 98 poly(2) VIOUT2 VI2 -19.803E-3 1 -1 FO3 0 400 VIOUT1 1 VI1 401 0 0 VI2 0 402 0 DM1 400 401 DX DM2 402 400 DX ********CURRENT MIRROR TO SUPPLIES NEGATIVE SIDE********* FO1B 0 99 poly(2) VIOUTB1 VIB1 -19.803E-3 1 -1 FO2B 0 98 poly(2) VIOUTB2 VIB2 -19.803E-3 1 -1 FO3B 0 400B VIOUTB1 1 VIB1 401B 0 0 VIB2 0 402B 0 DMB1 400B 401B DX DMB2 402B 400B DX .MODEL QX PNP (BF=228.57 Is=1E-15) .MODEL DX D(IS=1E-15) .ENDS AD8138 *$ * AD825 SPICE Macro-model 11/17/99, Rev. C * JCH / ADI Cent Apps * * Copyright 1999 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * *THIS MACROMODEL IS OPTIMIZED FOR POWER SUPPLIES OF 5V, WITH ASSOCIATED PARAMETERS *LISTED ON THE DATA SHEET. FOR 15V OPERATION, PLEASE USE THE AD825_15V MODEL. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD825_15V 1 2 99 50 30 * * INPUT STAGE & POLE AT 245 MHZ * R3 5 50 725 R4 6 50 725 C2 5 6 0.3E-12 I1 99 4 1.0E-3 J1 5 2 4 JX J2 6 3 4 JX Cin1 1 0 3E-12 Cin2 2 0 3E-12 Ios 1 2 20p Vos 1 3 1mV * EREF1 98 97 99 0 0.5 EREF2 97 0 50 0 0.5 * * GAIN STAGE & POLE AT 5.1 KHZ * R5 9 98 6.5E6 C3 9 98 4.6p G1 98 9 5 6 9.2E-4 V2 99 8 2.3 V3 10 50 2.25 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ R9 23 98 1E6 C8 23 98 0.8E-15 G5 98 23 9 98 1E-6 * * OUTPUT STAGE * R15 29 40 16 R16 29 41 16 L1 29 31 6E-12 V6 31 30 0 G7 29 40 99 23 6.25E-2 G8 41 29 23 50 6.25E-2 V4 25 29 0.2 V5 29 26 0.2 D3 23 25 DX D4 26 23 DX Vt1 99 40 0 Vt2 41 50 0 * *SUPPLY CURRENT CORRECTION * ISY 99 50 5.5m Fo1 98 110 V6 1 Do1 110 111 dx Do2 112 110 dx Vi1 111 98 0 Vi2 98 112 0 Fsy1 0 99 Vt1 1 Fsy2 99 0 Vi1 1 Fsy3 50 0 Vt2 1 Fsy4 0 50 Vi2 1 * * MODELS USED * .MODEL JX PJF(BETA=1.1E-3 VTO=-2.000 IS=5E-12) .MODEL DX D(IS=1E-15) .ENDS AD825_15V *$ * AD825 SPICE Macro-model 11/17/99, Rev. C * JCH / ADI Cent Apps * * Copyright 1999 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * *THIS MACROMODEL IS OPTIMIZED FOR POWER SUPPLIES OF 5V, WITH ASSOCIATED PARAMETERS *LISTED ON THE DATA SHEET. FOR 15V OPERATION, PLEASE USE THE AD825_15V MODEL. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD825_5V 1 2 99 50 30 * * INPUT STAGE & POLE AT 245 MHZ * R3 5 50 775 R4 6 50 775 C2 5 6 0.42E-12 I1 99 4 1.0E-3 J1 5 2 4 JX J2 6 3 4 JX Cin1 1 0 3pF Cin2 2 0 3pF Ios 1 2 2pA Vos 1 3 1mV * EREF1 98 97 99 0 0.5 EREF2 97 0 50 0 0.5 * * GAIN STAGE & POLE AT 14 KHZ * R5 9 98 4.1E6 C3 9 98 2.8p G1 98 9 5 6 4.9E-4 V2 99 8 2.35 V3 10 50 2.3 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R9 23 98 1E6 C8 23 98 0.8E-15 G5 98 23 9 98 1E-6 * * OUTPUT STAGE * R15 29 40 16 R16 29 41 16 L1 29 31 6E-12 V6 31 30 0 G7 29 40 99 23 6.25E-2 G8 41 29 23 50 6.25E-2 V4 25 29 0.09 V5 29 26 0.09 D3 23 25 DX D4 26 23 DX Vt1 99 40 0 Vt2 41 50 0 * *SUPPLY CURRENT CORRECTION * ISY 99 50 5.5m Fo1 98 110 V6 1 Do1 110 111 dx Do2 112 110 dx Vi1 111 98 0 Vi2 98 112 0 Fsy1 0 99 Vt1 1 Fsy2 99 0 Vi1 1 Fsy3 50 0 Vt2 1 Fsy4 0 50 Vi2 1 * * MODELS USED * .MODEL JX PJF(BETA=8E-4 VTO=-2.0 IS=5E-12) .MODEL DX D(IS=1E-15) .ENDS AD825_5V *$ * AD825 SPICE Macro-model 10/28/99, Rev. A * JCH / ADI Cent Apps * * Copyright 1999 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD825 1 2 99 50 30 * * INPUT STAGE & POLE AT 245 MHZ * R3 5 50 1084.2 R4 6 50 1084.2 C2 5 6 0.3E-12 I1 99 4 1.0E-3 J1 5 2 4 JX J2 6 3 4 JX Cin 1 0 3E-12 Ios 1 2 15p Vos 1 3 1mV * EREF1 98 97 99 0 0.5 EREF2 97 0 50 0 0.5 * * GAIN STAGE & POLE AT 1.92 KHZ -- GAIN REDUCED SLIGHTLY TO MATCH SLEW RATE * R5 9 98 6.9E6 C3 9 98 4.5p G1 98 9 5 6 4.9E-4 V2 99 8 6.1 V3 10 50 6.05 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ -- GAIN ADDED TO MAKE UP FOR REDUCED GAIN IN PREVIOUS STAGE * R9 23 98 1E6 C8 23 98 0.8E-15 G5 98 23 9 98 1.86E-6 * * OUTPUT STAGE * R15 29 40 16 R16 29 41 16 L1 29 31 6E-12 V6 31 30 0 G7 29 40 99 23 6.25E-2 G8 41 29 23 50 6.25E-2 V4 25 29 1.4 V5 29 26 1.4 D3 23 25 DX D4 26 23 DX Vt1 99 40 0 Vt2 41 50 0 * *SUPPLY CURRENT CORRECTION * ISY 99 50 5.5m Fo1 98 110 V6 1 Do1 110 111 dx Do2 112 110 dx Vi1 111 98 0 Vi2 98 112 0 Fsy1 0 99 Vt1 1 Fsy2 99 0 Vi1 1 Fsy3 50 0 Vt2 1 Fsy4 0 50 Vi2 1 * * MODELS USED * .MODEL JX PJF(BETA=4.25E-4 VTO=-2.000 IS=5E-12) .MODEL DX D(IS=1E-15) .ENDS AD825 *$ * OP250/OP450 SPICE Macro-Model Typcial Values * 10/97, Ver. 1 * TAM / ADSC * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP250 1 2 99 50 45 * * INPUT STAGE * M1 4 3 6 6 MNIN L=2u W=66u M2 5 2 6 6 MNIN L=2u W=66u M3 7 3 9 9 MPIN L=2u W=66u M4 8 2 9 9 MPIN L=2u W=66u RD1 99 4 5E3 RD2 99 5 5E3 RD3 7 50 5E3 RD4 8 50 5E3 VCM1 10 50 -.3 VCM2 99 11 -.3 D1 10 6 DX D2 9 11 DX EOS 3 1 POLY(3) (61,98) (73,98) (81,0) 3E-3 1 1 1 IOS 1 2 .25E-12 IBIAS1 6 50 700E-6 IBIAS2 99 9 700E-6 * * CMRR=60 dB, ZERO AT 20kHz * ECM1 60 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 60 61 159.2E3 RCM2 61 98 159 CCM1 60 61 50E-12 * * PSRR=90dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 50 * * INTERNAL VOLTAGE REFERENCE * RSY1 99 91 100E3 RSY2 50 90 100E3 VSN1 91 90 DC 0 EREF 98 0 (90,0) 1 GSY 99 50 POLY(1) (99,50) -1.81E-3 1.5E-5 * * VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 30 RN2 81 0 1 * * POLE AT 1.25MHz * G2 98 20 POLY(2) (4,5) (7,8) 0 5E-5 5E-5 R2 20 98 10E3 C2 20 98 12.7E-12 * * GAIN STAGE * G1 98 30 (20,98) 3.5E-4 R1 30 98 6.25E6 CF 30 45 135E-12 D4 31 99 DX D5 50 32 DX V1 31 30 0.7 V2 30 32 0.7 * * OUTPUT STAGE * M5 45 41 99 99 MPOUT L=2u W=6660u M6 45 42 50 50 MNOUT L=2u W=6660u EO1 99 41 POLY(1) (98,30) .9232 1 EO2 42 50 POLY(1) (30,98) .8914 1 * * MODELS * .MODEL MNIN NMOS(LEVEL=2,VTO=0.75,KP=20E-6,CGSO=0,KF=2.5E-31,AF=1) .MODEL MPIN PMOS(LEVEL=2,VTO=-0.75,KP=20E-6,CGSO=0,KF=2.5E-31,AF=1) .MODEL MNOUT NMOS(LEVEL=2,VTO=0.75,KP=30E-6,LAMBDA=0.04,CGSO=0) .MODEL MPOUT PMOS(LEVEL=2,VTO=-0.75,KP=20E-6,LAMBDA=0.04,CGSO=0) .MODEL DX D(IS=1E-16) .ENDS OP250 *$ * OP262 SPICE Macro-model * 7/96, Ver. 1 * TAM / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP262 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14,20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 (20,0) 1 G1 98 10 (5,6) 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 (10,98) .588E-6 R4 21 98 1.7E+6 R5 21 22 1.7E+6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 (21,98) 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 (24,98) 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY(1) (99,50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY(1) (98,25) 0.70366 1 EB2 42 50 POLY(1) (25,98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 .MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS OP262 *$ * OP281 SPICE Macro-model * 7/97, Ver. 1 * TAM / ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP281 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12,98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 (90,0) 1 G1 98 20 (4,6) 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 (20,98) 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8.5E-12 R5 40 98 65.65E6 G3 98 40 (22,98) 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 48 46 99 99 POX L=1.5u W=300u M2 49 47 50 50 NOX L=1.5u W=300u RO1 48 45 400 RO2 49 45 200 EG1 99 46 POLY(1) (98,40) 0.77 1 EG2 47 50 POLY(1) (40,98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS OP281 *$ * OP292G SPICE Macro-model Rev. A, 3/95 * ARG / ADSC * * This version of the OP292 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP292G 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 51.4E-6 IOS 2 1 25E-9 EOS 2 3 POLY(1) (21,30) 2E-3 16.8 CIN 1 2 2E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 965 R6 4 8 965 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 500E-6 R7 9 98 14.388E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 (13,30) 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 10 *C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 (9,30) 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .236E-3 G3 31 50 POLY(1) (16,30) -1.681511E-6 1E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCP 99 36 75 RCL 33 50 75 Q6 35 36 99 QPA Q7 32 37 50 QNA R17 35 37 1E3 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 0.23E-12 Q3 36 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 RC=400) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 RC=250) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6 WD=1E-6) .MODEL QP PNP(BF=35.714) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP292G *$ * OP295 SPICE Macro-model 2/95, Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Added common mode stage to base model. * Changed G1 to a polynomial source to correct output stage offset. * * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 0.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 30E-6 0.024 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.8E3 R4 9 50 25.8E3 * * GAIN STAGE * R7 10 98 270E6 G1 98 10 POLY(1) (9,8) -4.26712E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 100E3 R6 39 50 100E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 33 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 8 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 50E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=125) .ENDS OP295 *$ * OP295G SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP295 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295G 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS OP295G *$ * OP295A SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP295 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295A 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS OP295A *$ * OP296 SPICE Macro-model Rev. A, 5/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP296 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN 2 Q2 6 4 8 50 QN 2 Q3 4 4 7 50 QN 1 Q4 4 4 8 50 QN 1 Q5 50 1 7 99 QP 2 Q6 50 3 8 99 QP 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q7 99 1 9 50 QN 2 Q8 99 3 10 50 QN 2 Q9 12 11 9 99 QP 2 Q10 13 11 10 99 QP 2 Q11 11 11 9 99 QP 1 Q12 11 11 10 99 QP 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 0.75N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 251.641MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 10 * * OUTPUT STAGE * ISY 99 50 20E-6 EIN 35 50 POLY(1) (15,98) 1.42735 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QP 10 Q33 49 44 50 50 QN 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) .ENDS OP296 *$ * AD8517/AD8527 SPICE Macro-model * Typical Values * 11/99, Ver. 1 * Troy Murphy / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8517 1 2 99 50 45 * * RAIL-TO-RAIL INPUT STAGE * Q1 5 7 3 PIX Q2 6 2 4 PIX RC1 5 50 1780 RC2 6 50 1780 RE1 3 10 522 RE2 4 10 522 RCM1 10 99 1.15E+6 CCM1 10 99 3.08E-12 C1 5 6 2.9E-12 D1 3 8 DX D2 4 9 DX V1 99 8 DC 0.7 V2 99 9 DC 0.7 I1 99 10 225E-6 Q3 11 7 13 NIX Q4 12 2 14 NIX RC3 99 11 1780 RC4 99 12 1780 RE3 13 15 522 RE4 14 15 522 RCM2 15 50 1.15E+6 CCM2 15 50 3.08E-12 C2 11 12 2.9E-12 I2 15 50 225E-6 V3 16 50 DC 0.7 V4 17 50 DC 0.7 D3 16 13 DX D4 17 14 DX EOS 7 1 POLY(2) (73,98) (81,98) 1.3E-3 1 1 IOS 1 2 50E-9 * * PSRR=90dB, ZERO AT 100Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 50E-12 RPS4 73 98 480 * * VOLTAGE NOISE REFERENCE OF 12nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 12 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 56.1E-6 25E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * GAIN STAGE * G1 98 30 POLY(2) (5,6) (11,12) 0 0.8E-3 0.8E-3 R1 30 98 3.47E+5 CF 30 45 80E-12 D5 30 97 DX D6 51 30 DX * * RAIL-TO-RAIL OUTPUT STAGE * Q5 45 41 99 POUT Q6 45 43 50 NOUT EB1 99 40 POLY(1) (98,30) 0.7308 1 EB2 42 50 POLY(1) (30,98) 0.7308 1 RB1 40 41 500 RB2 42 43 500 D7 46 99 DX D8 47 43 DX V5 46 41 0.5 V6 47 50 0.5 * .MODEL NIX NPN (BF=280,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL PIX PNP (BF=560,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL POUT PNP (BF=100,IS=1E-16,VAF=130,RC=20) .MODEL NOUT NPN (BF=100,IS=1E-16,VAF=130,RC=11) .MODEL DX D(IS=1E-16,RS=5) .ENDS AD8517 *$ * AD8519/AD8529 SPICE Macro-model * 10/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8519 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 15 PIX Q2 6 2 15 PIX IOS 1 2 1.25E-9 I1 99 15 200E-6 EOS 7 1 POLY(2) (14,98) (73,98) 1E-3 1 1 RC1 5 50 2E3 RC2 6 50 2E3 C1 5 6 1.3E-12 D1 15 8 DX V1 99 8 DC 0.9 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 ISY 99 50 300E-6 * * CMRR=100dB, ZERO AT 1kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 13 14 1E6 RCM2 14 98 10 CCM1 13 14 240E-12 * * PSRR=100dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 15.9 * * POLE AT 20MHz, ZERO AT 60MHz * G1 21 98 (5,6) 5.88E-6 R1 21 98 170E3 R2 21 22 85E3 C2 22 98 40E-15 * * GAIN STAGE * G2 25 98 (21,98) 37.5E-6 R5 25 98 1E7 CF 45 25 5E-12 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * Q3 45 41 99 POUT Q4 45 43 50 NOUT EB1 99 40 POLY(1) (98,25) 0.594 1 EB2 42 50 POLY(1) (25,98) 0.594 1 RB1 40 41 500 RB2 42 43 500 * * MODELS * .MODEL PIX PNP (BF=500,IS=1E-14,KF=5E-6) .MODEL POUT PNP (BF=100,IS=1E-14,BR=0.517) .MODEL NOUT NPN (BF=100,IS=1E-14,BR=0.413) .MODEL DX D(IS=1E-14,CJO=1E-15) .ENDS AD8519 *$ * AD8531 SPICE Macro-model 7/97, Rev. A * ARG/TAM ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8531 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends AD8531 *$ * AD8532 SPICE Macro-model 3/96, Rev. A * 5-Volt Version ARG / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8532 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends AD8532 *$ * AD8534 SPICE Macro-model 7/97, Rev. A * ARG/TAM ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8534 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 rg=1 rb=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 rg=1 rb=1 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends AD8534 *$ * AD8541 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8541 1 2 99 50 45 * * INPUT STAGE * M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 RC1 4 50 20E3 RC2 6 50 20E3 RC3 99 11 20E3 RC4 99 12 20E3 C1 4 6 1.5E-12 C2 11 12 1.5E-12 I1 99 8 1E-5 I2 10 50 1E-5 V1 99 9 0.2 V2 13 50 0.2 D1 8 9 DX D2 13 10 DX EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 IOS 1 2 2.5E-12 * * CMRR 64dB, ZERO AT 20kHz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 79.6E3 CCM1 21 22 100E-12 RCM2 22 98 50 * * PSRR=90dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 25 * * VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 35 RN2 81 0 1 * * INTERNAL VOLTAGE REFERENCE * VFIX 90 98 DC 1 S1 90 91 (50,99) VSY_SWITCH VSN1 91 92 DC 0 RSY 92 98 1E3 EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 0 3.7E-6 * * ADAPTIVE GAIN STAGE * AT Vsy>+4.2, AVol=45 V/mv * AT Vsy<+3.8, AVol=450 V/mv * G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 VR1 30 31 DC 0 H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 CF 45 30 10E-12 D3 30 99 DX D4 50 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.6E-6 W=375E-6 M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 EG1 99 46 POLY(1) (98,30) 1.05 1 EG2 47 50 POLY(1) (30,98) 1.04 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL DX D(IS=1E-14) .MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) .ENDS AD8541 *$ * AD8542 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8542 1 2 99 50 45 * * INPUT STAGE * M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 RC1 4 50 20E3 RC2 6 50 20E3 RC3 99 11 20E3 RC4 99 12 20E3 C1 4 6 1.5E-12 C2 11 12 1.5E-12 I1 99 8 1E-5 I2 10 50 1E-5 V1 99 9 0.2 V2 13 50 0.2 D1 8 9 DX D2 13 10 DX EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 IOS 1 2 2.5E-12 * * CMRR 64dB, ZERO AT 20kHz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 79.6E3 CCM1 21 22 100E-12 RCM2 22 98 50 * * PSRR=90dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 25 * * VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 35 RN2 81 0 1 * * INTERNAL VOLTAGE REFERENCE * VFIX 90 98 DC 1 S1 90 91 (50,99) VSY_SWITCH VSN1 91 92 DC 0 RSY 92 98 1E3 EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 0 3.7E-6 * * ADAPTIVE GAIN STAGE * AT Vsy>+4.2, AVol=45 V/mv * AT Vsy<+3.8, AVol=450 V/mv * G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 VR1 30 31 DC 0 H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 CF 45 30 10E-12 D3 30 99 DX D4 50 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.6E-6 W=375E-6 M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 EG1 99 46 POLY(1) (98,30) 1.05 1 EG2 47 50 POLY(1) (30,98) 1.04 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL DX D(IS=1E-14) .MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) .ENDS AD8542 *$ * AD8544 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8544 1 2 99 50 45 * * INPUT STAGE * M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 RC1 4 50 20E3 RC2 6 50 20E3 RC3 99 11 20E3 RC4 99 12 20E3 C1 4 6 1.5E-12 C2 11 12 1.5E-12 I1 99 8 1E-5 I2 10 50 1E-5 V1 99 9 0.2 V2 13 50 0.2 D1 8 9 DX D2 13 10 DX EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 IOS 1 2 2.5E-12 * * CMRR 64dB, ZERO AT 20kHz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 79.6E3 CCM1 21 22 100E-12 RCM2 22 98 50 * * PSRR=90dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 25 * * VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 HN 81 0 VN1 35 RN2 81 0 1 * * INTERNAL VOLTAGE REFERENCE * VFIX 90 98 DC 1 S1 90 91 (50,99) VSY_SWITCH VSN1 91 92 DC 0 RSY 92 98 1E3 EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 0 3.7E-6 * * ADAPTIVE GAIN STAGE * AT Vsy>+4.2, AVol=45 V/mv * AT Vsy<+3.8, AVol=450 V/mv * G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 VR1 30 31 DC 0 H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 CF 45 30 10E-12 D3 30 99 DX D4 50 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.6E-6 W=375E-6 M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 EG1 99 46 POLY(1) (98,30) 1.05 1 EG2 47 50 POLY(1) (30,98) 1.04 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL DX D(IS=1E-14) .MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) .ENDS AD8544 *$ * AD8552 SPICE Macro-model * Typical Values * 7/99, Ver. 1.0 * TAM / ADSC * * Copyright 1999 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8552 1 2 99 50 45 * * INPUT STAGE * M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 RC1 4 14 9E+3 RC2 6 16 9E+3 RC3 17 11 9E+3 RC4 18 12 9E+3 RC5 14 50 1E+3 RC6 16 50 1E+3 RC7 99 17 1E+3 RC8 99 18 1E+3 C1 14 16 30E-12 C2 17 18 30E-12 I1 99 8 100E-6 I2 10 50 100E-6 V1 99 9 0.3 V2 13 50 0.3 D1 8 9 DX D2 13 10 DX EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 IOS 1 2 2.5E-12 * * CMRR 120dB, ZERO AT 20Hz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 50E+6 CCM1 21 22 159E-12 RCM2 22 98 50 * * PSRR=120dB, ZERO AT 1Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 10E-9 RPS4 73 98 16 * * VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 45 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 (99,50) 48E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * LHP ZERO AT 7MHz, POLE AT 50MHz * E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 R2 32 33 3.7E+3 R3 33 98 22.74E+3 C3 32 33 1E-12 * * GAIN STAGE * G1 98 30 (33,98) 22.7E-6 R1 30 98 259.1E+6 CF 45 30 45.4E-12 D3 30 97 DX D4 51 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=1E-6 W=1.111E-3 M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 EG1 99 46 POLY(1) (98,30) 1.1936 1 EG2 47 50 POLY(1) (30,98) 1.2324 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) .MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) .MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) .MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) .MODEL DX D(IS=1E-14,RS=5) .ENDS AD8552 *$ * AD8561 SPICE Macro-Model Typcial Values * 11/98, Ver. 2.1 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | Latch * | | | | | DGND * | | | | | | Q * | | | | | | | QNOT * | | | | | | | | .SUBCKT AD8561 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 1E-12 CIN 1 2 3E-12 VCM1 99 7 1 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltages * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=80dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 1 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 10E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section * GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 RSY 52 51 10 * * Gain Stage Av=250 fp=100MHz * G2 98 20 (12,98) 0.25 R1 20 98 1000 C1 20 98 10E-13 E3 97 0 (99,0) 1 E4 52 0 (51,0) 1 V1 97 21 DC 0.8 V2 22 52 DC 0.8 D2 20 21 DX D3 22 20 DX * * Q Output * Q3 99 41 46 NOX Q4 47 42 51 NOX RB1 43 41 200 RB2 40 42 200 CB1 99 41 10E-12 CB2 42 51 100E-12 RO1 46 44 1 D4 44 45 DX RO2 47 45 500 EO1 97 43 (20,51) 1 EO2 40 51 (20,51) 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 51 NOX RB3 63 61 200 RB4 60 62 200 CB3 99 61 10E-12 CB4 62 51 100E-12 RO3 66 64 1 D5 64 65 DX RO4 67 65 500 EO3 63 51 (20,51) 1 EO4 97 60 (20,51) 1 * * MODELS * .MODEL PIX PNP(BF=100,IS=1E-16) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-16) .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4) .ENDS AD8561 *$ * AD8564 SPICE Macro-Model Typical Values * 11/98, Ver. 2.1 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | ground * | | | | | output * | | | | | | .SUBCKT AD8564 1 2 99 50 51 45 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 2.5E-12 CIN 1 2 3E-12 EOS 3 1 (4,6) 1E-3 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RDUM 98 0 100E3 GSY 99 50 POLY(1) (99,50) 8E-3 -2.6E-3 * * Gain Stage Av=250 fp=100MHz * G1 98 20 (4,6) 0.25 R1 20 98 1E3 C1 20 98 10E-13 E3 97 0 (99,0) 1 E4 52 0 (51,0) 1 V1 97 21 DC 0.8 V2 22 52 DC 0.8 D1 20 21 DX D2 22 20 DX * * Output Stage * Q3 99 41 46 NOX Q4 47 42 51 NOX RB1 43 41 200 RB2 40 42 200 CB1 99 41 10E-12 CB2 42 51 100E-12 RO1 46 44 1 D4 44 45 DX RO2 47 45 500 EO1 97 43 (20,51) 1 EO2 40 52 (20,51) 1 * * MODELS * .MODEL PIX PNP(BF=100,VAF=130,IS=1E-14) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-14,CJO=1E-15) .ENDS AD8564 *$ * AD8572 SPICE Macro-model * Typical Values * 10/99, Ver. 1.0 * TAM / ADSC * * Copyright 1999 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8572 1 2 99 50 45 * * INPUT STAGE * M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 RC1 4 14 9E+3 RC2 6 16 9E+3 RC3 17 11 9E+3 RC4 18 12 9E+3 RC5 14 50 1E+3 RC6 16 50 1E+3 RC7 99 17 1E+3 RC8 99 18 1E+3 C1 14 16 30E-12 C2 17 18 30E-12 I1 99 8 100E-6 I2 10 50 100E-6 V1 99 9 0.3 V2 13 50 0.3 D1 8 9 DX D2 13 10 DX EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 IOS 1 2 2.5E-12 * * CMRR 120dB, ZERO AT 20Hz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 50E+6 CCM1 21 22 159E-12 RCM2 22 98 50 * * PSRR=120dB, ZERO AT 1Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 10E-9 RPS4 73 98 16 * * VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 51 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 (99,50) 48E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * LHP ZERO AT 7MHz, POLE AT 50MHz * E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 R2 32 33 3.7E+3 R3 33 98 22.74E+3 C3 32 33 1E-12 * * GAIN STAGE * G1 98 30 (33,98) 22.7E-6 R1 30 98 259.1E+6 CF 45 30 45.4E-12 D3 30 97 DX D4 51 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=1E-6 W=1.111E-3 M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 EG1 99 46 POLY(1) (98,30) 1.1936 1 EG2 47 50 POLY(1) (30,98) 1.2324 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) .MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) .MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) .MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) .MODEL DX D(IS=1E-14,RS=5) .ENDS AD8572 *$ * AD8591/92/94 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | shutdown * | | | | | | .SUBCKT AD8592 1 2 99 50 45 80 * * INPUT STAGE * M1 4 1 3 3 PIX L=0.8E-6 W=125E-6 M2 6 7 3 3 PIX L=0.8E-6 W=125E-6 RC1 4 50 4E3 RC2 6 50 4E3 C1 4 6 2E-12 I1 99 8 100E-6 M3 10 1 12 12 NIX L=0.8E-6 W=125E-6 M4 11 7 12 12 NIX L=0.8E-6 W=125E-6 RC3 10 99 4E3 RC4 11 99 4E3 C2 10 11 2E-12 I2 13 50 100E-6 EOS 7 2 POLY(3) (21,98) (73,98) (61,0) 1E-3 0 0 1 IOS 1 2 2.5E-12 V1 99 9 0.9 D1 3 9 DX V2 14 50 0.9 D2 14 12 DX S1 3 8 (82,98) SOPEN S2 99 8 (98,82) SCLOSE S3 12 13 (82,98) SOPEN S4 13 50 (98,82) SCLOSE * * CMRR 64dB, ZERO AT 20kHz * ECM1 20 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 20 21 79.6E3 CCM1 20 21 100E-12 RCM2 21 98 50 * * PSRR=80dB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 80 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 20E-6 10E-7 * * SHUTDOWN SECTION * E1 81 98 (80,50) 1 R1 81 82 1E3 C3 82 98 1E-9 * * VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz) * VN1 60 0 0 RN1 60 0 16.45E-3 HN 61 0 VN1 30 RN2 61 0 1 * * GAIN STAGE * G2 98 30 POLY(2) (4,6) (10,11) 0 2.19E-5 2.19E-5 R2 30 98 13E6 CF 45 30 5E-12 S5 30 98 (98,82) SCLOSE D3 30 31 DX D4 32 30 DX V3 99 31 0.6 V4 32 50 0.6 * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.8E-6 W=16E-3 M6 45 47 50 50 NOX L=0.8E-6 W=16E-3 EG1 99 48 POLY(1) (98,30) 1.06 1 EG2 49 50 POLY(1) (30,98) 1.05 1 RG1 48 46 10E3 RG2 49 47 10E3 S6 46 99 (98,82) SCLOSE S7 47 50 (98,82) SCLOSE * * MODELS * .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL POX PMOS (LEVEL=2,KP=8E-6,VTO=-1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=13.4E-6,VTO=1,LAMBDA=0.067) .MODEL SOPEN VSWITCH(VON=2.4,VOFF=0.8,RON=10,ROFF=1E9) .MODEL SCLOSE VSWITCH(VON=-0.8,VOFF=-2.4,RON=10,ROFF=1E9) .MODEL DX D(IS=1E-14) .ENDS AD8592 *$ * AD8598 SPICE Macro-Model Typcial Values * 11/98, Ver. 2.1 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | Latch * | | | | | DGND * | | | | | | Q * | | | | | | | QNOT * | | | | | | | | .SUBCKT AD8598 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 1E-12 CIN 1 2 3E-12 VCM1 99 7 1 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltages * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=80dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 1 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 10E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section * GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 RSY 52 51 10 * * Gain Stage Av=250 fp=100MHz * G2 98 20 (12,98) 0.25 R1 20 98 1000 C1 20 98 10E-13 E3 97 0 (99,0) 1 E4 52 0 (51,0) 1 V1 97 21 DC 0.8 V2 22 52 DC 0.8 D2 20 21 DX D3 22 20 DX * * Q Output * Q3 99 41 46 NOX Q4 47 42 51 NOX RB1 43 41 200 RB2 40 42 200 CB1 99 41 10E-12 CB2 42 51 100E-12 RO1 46 44 1 D4 44 45 DX RO2 47 45 500 EO1 97 43 (20,51) 1 EO2 40 51 (20,51) 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 51 NOX RB3 63 61 200 RB4 60 62 200 CB3 99 61 10E-12 CB4 62 51 100E-12 RO3 66 64 1 D5 64 65 DX RO4 67 65 500 EO3 63 51 (20,51) 1 EO4 97 60 (20,51) 1 * * MODELS * .MODEL PIX PNP(BF=100,IS=1E-16) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-16) .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4) .ENDS AD8598 *$ * AD8614/AD8644 SPICE Macro-model * Typical Values * 11/99, Ver. 1.1 * Troy Murphy / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8614 1 2 99 50 45 * * RAIL-TO-RAIL INPUT STAGE * Q1 5 7 3 PIX Q2 6 2 4 PIX Q3 11 7 13 NIX Q4 12 2 14 NIX RC1 5 50 2310 RC2 6 50 2310 RC3 99 11 2310 RC4 99 12 2310 RE1 3 10 620 RE2 4 10 620 RE3 13 15 620 RE4 14 15 620 I1 99 10 300E-6 I2 15 50 300E-6 RCM1 10 99 5.58E+5 RCM2 15 50 5.58E+5 CCM1 10 99 1.43E-11 CCM2 15 50 1.43E-11 C1 5 6 1.19E-12 C2 11 12 1.19E-12 D1 3 8 DX D2 4 9 DX D3 16 13 DX D4 17 14 DX V1 99 8 DC 0.7 V2 99 9 DC 0.7 V3 16 50 DC 0.7 V4 17 50 DC 0.7 EOS 7 1 POLY(2) (73,98) (81,98) 1E-3 1 1 IOS 1 2 10E-9 * * PSRR=100dB, ZERO AT 100Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 50E-12 RPS4 73 98 159 * * VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 10 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 41.121E-6 5E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * GAIN STAGE * G1 98 30 POLY(2) (5,6) (11,12) 0 3.125E-4 3.125E-4 R1 30 98 2.25E+6 CF 30 45 49E-12 D5 30 97 DX D6 51 30 DX * * RAIL-TO-RAIL OUTPUT STAGE * Q5 45 41 99 POUT Q6 45 43 50 NOUT EB1 99 40 POLY(1) (98,30) 0.7129 1 EB2 42 50 POLY(1) (30,98) 0.7129 1 RB1 40 41 500 RB2 42 43 500 D7 46 99 DX D8 47 43 DX V5 46 41 0.5 V6 47 50 0.5 * .MODEL NIX NPN (BF=220,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL PIX PNP (BF=220,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL POUT PNP (BF=100,IS=1E-16,VAF=200,RC=4) .MODEL NOUT NPN (BF=100,IS=1E-16,VAF=200,RC=4) .MODEL DX D(IS=1E-16,RS=5) .ENDS AD8614 *$ * AD8631/AD8632 SPICE Macro-model * Typical Values * 1/00, Ver. 1 * OEB / ADSC * * Copyright 2000 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8631 1 2 99 50 45 * * RAIL-TO-RAIL INPUT STAGE * Q1 5 7 3 PIX Q2 6 2 4 PIX RC1 5 50 6000 RC2 6 50 6000 RE1 3 10 435 RE2 4 10 435 RCM1 10 99 816E+3 CCM1 10 99 6.50E-12 C1 5 6 6.63E-12 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 I1 99 10 100E-6 Q3 11 7 13 NIX Q4 12 2 14 NIX RC3 99 11 6000 RC4 99 12 6000 RE3 13 15 435 RE4 14 15 435 RCM2 15 50 8.16E+5 CCM2 15 50 6.50E-12 C2 11 12 6.63E-12 I2 15 50 100E-6 V3 16 50 DC 1 V4 17 50 DC 1 D3 16 13 DX D4 17 14 DX EOS 7 1 POLY(2) (73,98) (81,98) 0.8E-3 1 1 IOS 1 2 75E-9 * * PSRR=90dB, ZERO AT 100Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 50E-12 RPS4 73 98 480 * * VOLTAGE NOISE REFERENCE OF 12nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 12 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 POLY(1) (99,50) 56.1E-6 25E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * GAIN STAGE * G1 98 30 POLY(2) (5,6) (11,12) 0 0.25E-3 0.25E-3 R1 30 98 2.3E+5 CF 30 45 100E-12 D5 30 97 DX D6 51 30 DX * * RAIL-TO-RAIL OUTPUT STAGE * Q5 45 41 99 POUT Q6 45 43 50 NOUT EB1 99 40 POLY(1) (98,30) 0.7129 1 EB2 42 50 POLY(1) (30,98) 0.7129 1 RB1 40 41 500 RB2 42 43 500 D7 46 99 DX D8 47 43 DX V5 46 41 0.5 V6 47 50 0.5 * .MODEL NIX NPN (BF=200,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL PIX PNP (BF=200,IS=1E-16,VAF=130,KF=2.5E-14) .MODEL POUT PNP (BF=1000,IS=1.075E-16,VAF=130,RC=20) .MODEL NOUT NPN (BF=1000,IS=1.075E-16,VAF=130,RC=11) .MODEL DX D(IS=1E-16,RS=5) .ENDS AD8631 * *$ * OP462 SPICE Macro-model * 7/96, Ver. 1 * TAM / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP462 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14,20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 (20,0) 1 G1 98 10 (5,6) 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 (10,98) .588E-6 R4 21 98 1.7E+6 R5 21 22 1.7E+6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 (21,98) 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 (24,98) 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY(1) (99,50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY(1) (98,25) 0.70366 1 EB2 42 50 POLY(1) (25,98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 .MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS OP462 *$ * OP481 SPICE Macro-model * 7/97, Ver. 1 * TAM / ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP481 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12,98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 (90,0) 1 G1 98 20 (4,6) 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 (20,98) 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8.5E-12 R5 40 98 65.65E6 G3 98 40 (22,98) 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 48 46 99 99 POX L=1.5u W=300u M2 49 47 50 50 NOX L=1.5u W=300u RO1 48 45 400 RO2 49 45 200 EG1 99 46 POLY(1) (98,40) 0.77 1 EG2 47 50 POLY(1) (40,98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS OP481 *$ * OP492G SPICE Macro-model Rev. A, 3/95 * ARG / ADSC * * This version of the OP492 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP492G 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 51.4E-6 IOS 2 1 25E-9 EOS 2 3 POLY(1) (21,30) 2E-3 16.8 CIN 1 2 2E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 965 R6 4 8 965 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 500E-6 R7 9 98 14.388E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 (13,30) 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 10 *C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 (9,30) 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .236E-3 G3 31 50 POLY(1) (16,30) -1.681511E-6 1E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCP 99 36 75 RCL 33 50 75 Q6 35 36 99 QPA Q7 32 37 50 QNA R17 35 37 1E3 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 0.23E-12 Q3 36 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 RC=400) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 RC=250) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6 WD=1E-6) .MODEL QP PNP(BF=35.714) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP492G *$