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\title{\bf MECHTRON 3TB4 - Embedded Systems II}

\author{}
\date{}
\begin{document}


\maketitle

\vspace{-1.5cm}

\subsection*{COURSE WEBSITE:}
\url{http://elm.mcmaster.ca/}

\vspace{1.0cm}


\begin{minipage}[t]{3.0in}
\subsection*{INSTRUCTOR:} Dr. Mark Lawford\\ Office: ITB/160 \\
E-mail: lawford@mcmaster.ca\\ 
Office Hours: TBA
\end{minipage}
\begin{minipage}[t]{3.0in}
\subsection*{Teaching Assistants:} Honghan Deng \& Alvin Ihsani\\
Email:	dengh, ihsania@mcmaster.ca\\
Office: ITB/205 TBA
 \end{minipage}

\subsection*{LECTURES:}
Location: BSB/108 \hspace{1.0cm} Time: Mon, Wed 11:30-12:20, Fri 13:30-14:20

\subsection*{TUTORIALS \& LABS:}
Location: ITB/238 (NOTE THESE MAY CHANGE FROM CURRENT TIMETABLE!)

Time: \begin{tabular}{|c|c|c|}\hline
  Section& Tutorial Time    & Lab Time\\\hline\hline
  1      & Mon 9:30-11:20 & Tues 08:30-11:20\\\hline
  2      & Wed 14:30-16:20 & Mon 14:30-17:20\\\hline
\end{tabular}


\subsection*{DESCRIPTION:}

Design and implementation of embedded systems interacting with analog systems. Software design and implementation for embedded systems and DSP systems. Simulation and testing of embedded systems. 


\subsection*{MISSION:}

\begin{itemize}

\item To connect theory with practice in the design and development of embedded control systems
\item To understand the importance of the ``environment'' (system under control - a.k.a. ``the plant'') and how to interface to it
\item To explore technologies used to build embedded systems. 	
\item To explore different components of embedded systems (e.g. memory system,
microprocessor architecture, bus protocols...) in depth. 
\item To learn how to build embedded hardware at a low level (RTL). 
\item To explore hardware/software trade-offs in embedded system design. 
\item Gain hands on experience in the design and development of FPGA based systems.
\item To have fun building various embedded systems.
\end{itemize}

\subsection*{TENTATIVE SCHEDULE OF TOPICS:}

The following schedule of topics and labs is tentative.  The instructor reserves the right to modify the schedule and lab topics depending up availability of equipment \& progress of the class.  \emph{Please be sure to check the course website regularly for updates}.

\begin{itemize}
\item  Introduction: Hardware Software co-design
    \item Stepper Motors and how to control them
    \item Interrupts
    \item Review of Digital Design Concepts
    \item Introduction to Verilog HDL
    \item Introduction to CAD tools for design, simulation, testing and debugging of embedded systems
    \item Introduction to IC manufacturing technologies
    \item Details of field programmable devices (PAL, PLA, CPLDs, FPGAs)
    \item Interfaces and bus protocols
    \item Memory Hierarchy
    \item Microprocessor Architecture
    \item Use of Finite State Machines to express the behaviour of digital systems
    \item Digital Signal Processing and introduction to digital filters
    \item Testing of Embedded Systems
\end{itemize}
  
\subsection*{GRADING:}

Two marking schemes are provided.  In order to have your assignments
count in your final mark (Scheme A), you must pass (obtain $\geq 50\%$) on
the combination of your midterm and final (Scheme B).  Provided you pass by Scheme B *AND* you completed all of the labs, your final mark will be the max(Scheme A, Scheme B).  Otherwise your mark will be min(Scheme A, Scheme B).  

\begin{tabular}{|lr|}
\multicolumn{2}{c}{Scheme A}\\\hline\hline
Midterm exam (1-2 hours)&20\%\\
Labs &30\%\\
Tutorial Exercises & 5\%\\
Final exam (3 hours) &45\%\\\hline
\end{tabular} or
\begin{tabular}{|lr|}
\multicolumn{2}{c}{Scheme B}\\\hline\hline
Midterm exam (1-2 hours)&30\%\\
Labs &0\%\\
Tutorial Exercises & 5\%\\
Final exam (3 hours) &65\%\\\hline
\end{tabular}


%\begin{tabular}{|lr|}\hline
%Tutorial Exercises& 5\%\\\hline
%Labs &30\%\\\hline
%Midterm exam (2 hours)&20\%\\\hline
%Final exam (3 hours) &45\%\\\hline
%\end{tabular} 

The instructor reserves the right to conduct deferred examinations orally.

One lab report will be submitted and marked for each group and all team members will receive the same mark unless there is a demonstrable lack of participation/effort by a team member in performing and writing up the work.  In that case the lab report grade will be assigned to individual team members based upon their contribution as judged by the TAs and Instructor.

%\pagebreak

\subsection*{TEXTS:}

\begin{enumerate}
\item\label{ESD} Frank Vahid
Tony D. Givargis, \textit{Embedded System Design: A Unified Hardware/Software Introduction}, John Wiley \& Sons, 2002.
ISBN: 978-0-471-38678-0 - AKA ``Vahid''

\item\label{AVR} Richard H. Barnett, P.E., Ph.D.; Sarah Cox; Larry O'Cull, 
\textit{Embedded C Programming and the Atmel AVR}, 2nd Edition, Thomson, 2007.
ISBN 13: 9781418039592, 
ISBN 10: 1418039594 - AKA ``Barnett''

\end{enumerate}



\subsection*{ADDITIONAL REFERENCES:}

\begin{itemize}
\item Robert B. Reese and Mitchell A. Thornton, \textit{Introduction to Logic Synthesis using Verilog HDL}, A Publication in the Morgan \& Claypool Publishers’ series
SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS \#6, 2006. ISBN-10: 1598291076 (ebook) 1598291068 (paperback) \url{http://www.morganclaypool.com/doi/abs/10.2200/S00060ED1V01Y200610DCS006}.

\item James K Peckol, \textit{Embedded Systems: A Contemporary Design Tool}, John Wiley \& Sons Inc., 2008. ISBN 978-0-471-72180-2 

\item Zainalabedin Navabi, \textit{Embedded Core Design with FPGAs}, McGraw Hill, 2007, ISBN 978-0-07-148470-1.

\item Stephen Brown and Zvonko Vranesic, \textit{Fundamentals of Digital Logic with Verilog Design}, 2nd edition, Boston: McGraw-Hill Higher Education, 2008., ISBN: 978-0077211646

\item Joe Pardue, \textit{C Programming for Microcontrollers Featuring ATMEL's AVR Butterfly and the free WinAVR Compiler}, Smiley Micros, 2005.
ISBN-10: 0976682206
ISBN-13: 978-0976682202

\item\label{CP} MECHTRON 3TA4 Course Pack (Available at the bookstore). - AKA ``CP''
\end{itemize}

\subsection*{CALCULATOR:}
Only the McMaster Standard Calculator will be permitted in tests and examinations. This is available at the McMaster
Bookstore.

\subsection*{NOTES:}

\subsubsection*{Announcements \& Updates:}

Announcements, updates and other important information will be done in class and via the course website.  You may be informed of announcements via your McMaster email account.  You are expected to attend classes, tutorials and labs where these announcements will be made.  If you miss a class, lecture or lab, \emph{it is your responsibility to check these resources and stay informed!}

\subsubsection*{Missed Lab Work:}

Lab work missed due to illness or personal circumstances may be made up. You must submit appropriate
documentation (e.g. note from physician) to your Faculty/Program office. It is your responsibility to follow-up with the
lab supervisor. No mark will be entered for the missed work unless the Faculty/Program office gives its approval.

\subsubsection*{Academic Dishonesty:}

You are expected to exhibit honesty and use ethical behavior in all aspects of the learning process.
Academic credentials you earn are rooted in principles of honesty and academic integrity.
Academic dishonesty is to knowingly act or fail to act in a way that results or could result in unearned
academic credit or advantage. This behavior can result in serious consequences, e.g. the grade of zero
on an assignment, loss of credit with a notation on the transcript (notation reads: ``Grade of F assigned for
academic dishonesty''), and/or suspension or expulsion from the university.
It is your responsibility to understand what constitutes academic dishonesty. For information on the various
types of academic dishonesty please refer to the Academic Integrity Policy, located at
\url{http://www.mcmaster.ca/academicintegrity}
The following illustrates only three forms of academic dishonesty:
\begin{enumerate}
\item                Plagiarism, e.g.\ the submission of work that is not one’s own or for which other credit has
                  been obtained.
\item                Improper collaboration in group work.
\item                Copying or using unauthorized aids in tests and examinations.
\end{enumerate}
In case of discrepancy between the online and handout version of the course outline, the handout version shall be
taken as correct.

\subsubsection*{Disclaimer}

The instructor and university reserve the right to modify elements of the
course during the term. The university may change the dates and deadlines
for any or all courses in extreme circumstances. If either type of
modification becomes necessary, reasonable notice and communication with the
students will be given with explanation and the opportunity to comment on
changes. It is the responsibility of the student to check their McMaster
email and course websites weekly during the term and to note any changes

%\subsection*{BONUS MARKS}

%At the discretion of the instructor, a student will receive 1 to 2
%``bonus marks'' on their latest lab or quiz for being the first person
%to point out a technical error in the lecture slides or other course
%related material or providing a particularly useful course resource.

\subsection*{FORMAT:}
   \begin{itemize}
 \item The class has lectures three times per week. Discussion is encouraged in class.

   \item There will be hands-on tutorials or labs alternate weeks. 

   \item Discussion groups, links to resources, grading, lecture slides, lab handouts and other course related material will be available through WebCT. 
   \item Students will submit their source code and lab reports via a course subversion version control repository unless otherwise indicated.
   \item Lab work will be done in groups of 2-3 students to be determined by the Instructor.  
   \end{itemize}
   
%\pagebreak
  
% \vspace{1.0cm}

% \begin{tabular}{|c|c|c|l|c|}\hline     
% \multicolumn{2}{|c|}{Week}&Topic& Reference& Lab Exercise\\
% Num& Begins& & & \\\hline\hline
%  1  &Sep 10&Intro&Vahid Ch 1 & None\\\hline
%  2  &Sep 14&Architecture &\parbox[t]{1.5in}{Vahid Ch 2\&3\\ Barnett Ch 1} &None\\\hline
%  3  &Sep 21&A/D, D/A \& Sensors &\parbox[t]{1.5in}{Vahid Ch 3,\\CP p. 179-197, 52-70}&Blinking Lights\\\hline% - Reading A
% nalog and Digital sensors Encoder position sensor
%  4  &Sep 28&Peripherals \& AVR &\parbox[t]{1.5in}{Vahid Ch 4\\ Barnett Ch 2 \& 4} & \\\hline
%  5  &Oct 5&Peripherals \& AVR &\parbox[t]{1.5in}{Vahid Ch 4\\ Barnett Ch 2 \& 4} &LCD controller\\\hline
%  6  &Oct 12& Interfacing&\parbox[t]{1.5in}{Vahid Ch 6\\ Barnett Ch 2 \& 3} & \\\hline
%  7  &Oct 19&\parbox[t]{1.5in}{Actuators \& Component Interconnection}&\parbox[t]{1.5in}{Vahid 4.7\\CP p. 1- 26, 74-100}&MIDTERM \\\hline
%  8  &Oct 26& \parbox[t]{1.5in}{Component Interconnect \& Signal Conditioning}&CP p. 70-73, 26-43&Serial Interfacing\\\hline%(SPI or I2C)
%  9  &Nov 2&Isolation \& PWM &\parbox[t]{1.5in}{Vahid 4.7\\CP p. 199-202} & \\%Motor control\\\hline%/optical isolation/PWM/Passive LPF Fan controller\\\hline
%  10 &Nov 9&Signal Conditioning &CP p. 26-52 & \\\hline
%  11 &Nov 16&Performance Spec \& Anal&CP. 119-178  &Stepper Motor\\\hline
%  12 &Nov 23&Performance \& PID &Vahid Ch. 9 & \\\hline
%  13 &Nov 30&Design \& Documentation &\parbox[t]{1.5in}{Barnett Ch 5\\Lecture slides} & None\\\hline
% % 14 &Dec 1  &Review/Catchup &All &None \\\hline
% \end{tabular}

\end{document}


