From: Subject: Exception and Interrupt Controller Date: Tue, 30 Dec 2008 11:45:07 -0500 MIME-Version: 1.0 Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Content-Location: http://www.johnloomis.org/NiosII/interrupts/exception.html X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 Exception and Interrupt Controller

Exception and Interrupt Controller

Control Registers

The Nios II architecture supports up to 32 = control=20 registers. Those involved in exception and interrupt processing are = shown below.=20

Register Name Register Contents=20
0 status status=20 controls the state of the Nios II processor=20
1 estatus holds a copy of the status register during non-break exception=20 processing.=20
2 bstatus holds a copy of the status register during break exception = processing.=20
3 ienable Interrupt-enable bits (see ienable)=20
4 ipending Pending-interrupt bits (see ipending=20

The status Register

Bits Field Description=20
31:3
Reserved=20
2 EH EH is the exception handler bit. The processor sets EH to one = when an=20 exception occurs (including breaks). Software clears EH to zero = when ready=20 to handle exceptions again. EH is used by the MMU to determine = whether a=20 TLB miss exception is a fast TLB miss or a double TLB miss. In = systems=20 without an MMU, EH is always zero.=20
1 U U is the user mode bit. When U =3D 1, the processor operates in = user=20 mode. When U =3D 0, the processor operates in supervisor mode. In = systems=20 without an MMU, U is always zero.=20
0 PIE PIE is the processor interrupt-enable bit. When PIE =3D 0, = interrupts=20 are ignored. When PIE =3D 1, interrupts can be taken, depending on = the value=20 of the ienable register.

The ienable Register

The ienable register controls the handling of external = hardware=20 interrupts. Each bit of the ienable register corresponds to one of the = interrupt=20 inputs, irq0 through irq31. A value of one in bit = n=20 means that the corresponding irqn interrupt is enabled; a bit = value of=20 zero means that the corresponding interrupt is disabled. See = =93Exception=20 Processing=94 on page 3=9634 for more information.=20

The ipending Register

The value of the ipending register indicates the value of = the=20 interrupt signals driven into the processor. A value of one in bit = n=20 means that the corresponding irqn input is asserted. Writing a = value to=20 the ipending register has no effect.=20

Control Instructions

Instruction Description=20
trap
eret 		The trap and eret instructions generate and = return=20 from exceptions. These instructions are similar to the call/ret = pair, but=20 are used for exceptions. trap saves the status = register=20 in the estatus register, saves the return address in the=20 ea register, and then transfers execution to the general=20 exception handler. eret returns from exception processing = by=20 restoring status from estatus, and executing the = instruction specified by the address in ea.=20
break
bret 		The break and bret instructions generate and = return=20 from breaks. break and bret are used exclusively = by=20 software debugging tools. Programmers never use these instructions = in=20 application code.=20
rdctl
wrctl 		These instructions read and write control registers, such as the = status register. The value is read from or stored to a=20 general-purpose register.=20
flushd
flushda
flushi
initd
initda
initi=20 		These instructions are used to manage the data and instruction = cache=20 memories.=20
flushp This instruction flushes all pre-fetched instructions from the=20 pipeline. This is necessary before jumping to recently-modified=20 instruction memory.=20
sync This instruction ensures that all previously-issued operations = have=20 completed before allowing execution of subsequent load and store=20 operations.

Exception Controller

The Nios II architecture provides a simple, non-vectored exception = controller=20 to handle all exception types. Each exception, including hardware = interrupts,=20 causes the processor to transfer execution to an exception address. An = exception=20 handler at this address determines the cause of the exception and = dispatches an=20 appropriate exception routine.=20

Exception addresses are specified in SOPC Builder at system = generation time.=20

All exceptions are precise. Precise means that the processor has = completed=20 execution of all instructions preceding the faulting instruction and not = started=20 execution of instructions following the faulting instruction. Precise = exceptions=20 allow the processor to resume program execution once the exception = handler=20 clears the exception.=20

Integral Interrupt Controller

The Nios II architecture supports 32 external hardware interrupts. = The=20 processor core has 32 level-sensitive interrupt request (IRQ) inputs, = irq0=20 through irq31, providing a unique input for each interrupt source. IRQ = priority=20 is determined by software. The architecture supports nested interrupts.=20

The software can enable and disable any interrupt source individually = through=20 the ienable control register, which contains an interrupt-enable bit for = each of=20 the IRQ inputs. Software can enable and disable interrupts globally = using the=20 PIE bit of the status control register. A hardware interrupt is = generated if and=20 only if all three of these conditions are true:=20

Interrupt Vector Custom Instruction

The Nios II processor core offers an interrupt vector custom = instruction=20 which accelerates interrupt vector dispatch. Include this custom = instruction to=20 reduce your program's interrupt latency.=20

The interrupt vector custom instruction is based on a priority = encoder with=20 one input for each interrupt connected to the Nios II processor. The = cost of the=20 interrupt vector custom instruction depends on the number of interrupts=20 connected to the Nios II processor. The worst case is a system with 32=20 interrupts. In this case, the interrupt vector custom instruction = consumes about=20 50 logic elements (LEs).=20

If you have a large number of interrupts connected, adding the = interrupt=20 vector custom instruction to your system might lower = fMAX.=20

Processing Interrupt and Instruction-Related Exceptions

Except for the break instruction (see =93Processing a Break=94 on = page 3-38),=20 this section describes the actions the processor takes in response to = interrupt=20 and instruction-related exceptions. Table 3-32 lists all possible = non-break=20 exception processing actions performed by hardware. Check marks indicate = which=20 actions apply to each of the processor scenarios, namely, systems = without an=20 MMU, systems with an MMU, and systems with an MMU that is currently = processing=20 an exception. For systems with an MMU, status.EH indicates = whether or=20 not exception processing is already in progress. When status.EH = =3D 1,=20 exception processing is already in progress and the states of the = exception=20 registers are preserved to retain the original exception states.=20

Processor Actions (no MMU)

Maintained by John Loomis, = last=20 updated 10 November 2008