Optimal Design of Analog Circuits via Geometric Programming
Joint work with Mar Hershenson and Tom Lee
There is a huge and growing industrial infrastructure for designing and manufacturing integrated circuits (ICs), mostly using complementary metal-oxide semiconductor (CMOS) devices, for digital circuits. A new and accelerating trend is towards mixed-signal ICs, which incorporate some analog functionality (such as data conversion or synchronization circuits) on the same IC, along with the digital circuitry. This increase in the design of mixed-signal ICs is greatly increasing the demand for analog CMOS design: not only will the number of new designs increase, but so will the number of designs that must be ported every 12 months or so to the newest IC process technology. This increase in demand comes during a great shortage of experienced analog designers. Predictions abound that analog design will become a critical bottleneck for next-generation system-on-a-chip (SoC) designs. In this talk I will describe a new general method for optimized design of analog CMOS circuit blocks, based on geometric programming (GP). The result is a method that can very efficiently determine globally optimal circuit designs, given specifications (such as on power, area, open-loop gain, bandwidth, etc.). The method can be used for rapid design, performance and trade-off analysis, and porting of analog circuit cells to new technologies. I will start with some general background (for the non-expert) on ICs and CMOS design. I will then describe GP, its conversion to a nonlinear but convex problem, and interior-point methods for GP. I will then explain how the method applies to the design of a simple circuit.