Final Review

Ch 2 to Ch 4. See Midterm Review

Ch 5. Processor: Datapath and Control

  • Major components of a processor: ALU, memory, register file, MUXs
  • Design of single-cycle processor: datapath
  • Design of multicycle processor: control
  • Finite state machine
  • Implementations: ROM, PLA, sequencer

    • Ch 6. Pipelining

  • Datapath
  • Resource conflict (PC adder, branch target, IM, ID)
  • Pipeline registers
  • Control: Extend pipeline registers, pass control signals
  • Data hazards: Detection, stall, forwarding
  • Branch hazards: Branch delay

    • Ch 7. Memory Hierarchy

  • Two types of locality: Temporal, spatial
  • Memory unit: block (single-word, multiword)
  • Cache
  • Mapping: direct, set associative, implementations
  • Replacement: LRU
  • Misses: three Cs
  • Performance: miss rate, miss penalty
  • Memory banks

    • Appendix C

  • Implementing combinational control units
  • ALU control
  • Main control (PLA)
  • Implementing finite state machine control
  • ROM implementation of functions
  • PLA implementation of functions
  • Sequencer implementation of the next-state function